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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 26.3. TCON: Timer Control
Bit
Name
Type
Reset
7
TF1
R/W
0
6
TR1
R/W
0
5
TF0
R/W
0
4
TR0
R/W
0
3
IE1
R/W
0
2
IT1
R/W
0
1
IE0
R/W
0
0
IT0
R/W
0
SFR Address = 0x88; SFR Page = All Pages; Bit-Addressable
Bit Name Function
7
6
5
4
3
2
1
0
270
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 16.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 16.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.4
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